Polelo ea boinotšing: Lekunutu la hau le bohlokoa haholo ho rona. Khamphani ea rona e tšepisa hore ha e etse hore u se ke ua senola tlhahisoleseling ea hau ho ea pele.
Setšoantšo sa No.: NSO4GU3AB
Lipalangoang: Ocean,Air,Express,Land
Mofuta oa Lekhetho: L/C,T/T,D/A
Incoterm: FOB,EXW,CIF
4GB 1600MHHZ 240-PIN DDR3 UDIMM
Ntlafatso Nalane
Revision No. |
History |
Draft Date |
Remark |
1.0 |
Initial Release |
Apr. 2022 |
|
Ho odara tafole ea tlhaiso-leseling
Model |
Density |
Speed |
Organization |
Component Composition |
NS04GU3AB |
4GB |
1600MHz |
512Mx64bit |
DDR3 256Mx8 *16 |
Tlhaloso
Li-hychroffied DDR3 sdram dimm (Tekanyetso ea memo e tlase habeli NS04gu3ab ke 512m-bit tse peli tsa xgb ddr3-1600 cl1 1,5v sdram SPD e hlophisitsoe ho Jedec Standard DDRY DDR3-1600 Nako ea 11-11-11 ka 1.5v. Demimm e ngoe le e ngoe ea 20 e sebelisa menoana ea mabitso ea khauta. SDRAM e sa sebetsoeng e etselitsoe ho sebelisoa e le memori e meholo ha e kenngoa litsamaiso tse kang li-PC le Mesebetsi ea Mesebetsi.
Likaroloana
Phepelo ea power: VDD = 1.5v (1.425v ho 1.575v)
vddq = 1.5v (1.425v ho 1.575v)
800MHZ Fck bakeng sa 1600BB / Sec / PIN
8 e ikemetseng e ntle
proGRAMMABSA CAS LAGON: 11, 9, 9, 7, 6
proGgraMMALD EXPPITATERable: 0, CL - kapa CL - Clack 1
8-bit Pre-Fet-Fetch
000 ...
Zimellang e fapaneng ea data ea data
inyast (Boitšoaro); Calibration ea ka hare ea kahare ka zq phini ea zq (rzq: 240 ohm ± 1%)
on Die Terries u sebelisa PINT EDT PIN
ajekrea e khathollang
usnchronous reset
Polotso ea Drive ea data ea data
Fly-ka topology
pcb: bophahamo ba 1.18 "(30mm)
rohs e lumellanang le halogen-free
Paramente ea Nako ea Nako
MT/s |
tRCD(ns) |
tRP(ns) |
tRC(ns) |
CL-tRCD-tRP |
DDR3-1600 |
13.125 |
13.125 |
48.125 |
2011/11/11 |
Tafole ea aterese
Configuration |
Refresh count |
Row address |
Device bank address |
Device configuration |
Column Address |
Module rank address |
4GB |
8K |
32K A[14:0] |
8 BA[2:0] |
2Gb (256 Meg x 8) |
1K A[9:0] |
2 S#[1:0] |
Litlhaloso tsa Pic
Symbol |
Type |
Description |
Ax |
Input |
Address inputs: Provide the row address for ACTIVE commands, and the column |
BAx |
Input |
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or |
CKx, |
Input |
Clock: Differential clock inputs. All control, command, and address input signals are |
CKEx |
Input |
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry |
DMx |
Input |
Data mask (x8 devices only): DM is an input mask signal for write data. Input data is |
ODTx |
Input |
On-die termination: Enables (registered HIGH) and disables (registered LOW) |
Par_In |
Input |
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. |
RAS#, |
Input |
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being |
RESET# |
Input |
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and |
Sx# |
Input |
Chip select: Enables (registered LOW) and disables (registered HIGH) the command |
SAx |
Input |
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address |
SCL |
Input |
Serial |
CBx |
I/O |
Check bits: Used for system error detection and correction. |
DQx |
I/O |
Data input/output: Bidirectional data bus. |
DQSx, |
I/O |
Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; |
SDA |
I/O |
Serial |
TDQSx, |
Output |
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD |
Err_Out# |
Output (open |
Parity error output: Parity error found on the command and address bus. |
EVENT# |
Output (open |
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical |
VDD |
Supply |
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The |
VDDSPD |
Supply |
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V. |
VREFCA |
Supply |
Reference voltage: Control, command, and address VDD/2. |
VREFDQ |
Supply |
Reference voltage: DQ, DM VDD/2. |
VSS |
Supply |
Ground. |
VTT |
Supply |
Termination voltage: Used for control, command, and address VDD/2. |
NC |
– |
No connect: These pins are not connected on the module. |
NF |
– |
No function: These pins are connected within the module, but provide no functionality. |
Lintlha : Lethathamo la Tlhatlhobo ea PIN ke lenane le felletseng ke lenane le felletseng la lipina tsohle tsa DDR3. Lintho tsohle li thathamisitsoe se ke oa tšehetsoa ho mojule ona. Sheba likabelo tsa DIN bakeng sa tlhaiso-leseling e ikhethang ho mojule ona.
Sesebelisoa sa S60l sa Thibelo
4GB, Module oa 512MMX64 (2rank of X8)
Mefuta ea Module
Sheba
Sheba
Lintlha:
1. Boholo bo ka millimeter (inches); Max / min kapa min kapa e tloaelehileng) moo ho hlokometsoeng teng.
2.Tolelarance ka boholo bohle ± 0.15mmmm ntle le ha e hlalositsoe ka tsela e 'ngoe.
3. Timani ea likarolo tse fapaneng tsa ho bua feela.
Lihlopha tsa Meriana : Setshelo sa Module oa Sepis
Polelo ea boinotšing: Lekunutu la hau le bohlokoa haholo ho rona. Khamphani ea rona e tšepisa hore ha e etse hore u se ke ua senola tlhahisoleseling ea hau ho ea pele.
Tlatsa tlhaiso-leseling e eketsehileng e le hore e ka ikopanya le uena kapele
Polelo ea boinotšing: Lekunutu la hau le bohlokoa haholo ho rona. Khamphani ea rona e tšepisa hore ha e etse hore u se ke ua senola tlhahisoleseling ea hau ho ea pele.